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A. EMC and Reliability
1. Is the deployment rate 100%
2. Has the clock line, differential pair, and high-speed signal line met the (SI constraint) requirements
3. Is the impedance of each layer of the high-speed signal line consistent
4. Have all types of BUS met the requirements of (SI constraint)
5. Have the E1, Ethernet, serial port and other interface signals met the requirements
6. Clock line, high-speed signal line and sensitive signal line shall not cross the Plane of reference to form a large signal loop
7. Can the power and ground carry sufficient current
8. (Estimation method: 1A/mm line width for outer copper thickness of 1oz, 0.5A/mm line width for inner layer, double short line current)
9. The power and ground leads on the chip are led out from the solder pad and connected to the nearby power and ground plane, with a line width of ≥ 0.2mm (8mil),
10. Try to achieve ≥ 0.25mm (10mi1)
11. There should be no isolated islands or narrow channels in the power supply and strata
12. Is the design of the working ground (digital and analog), protective ground, electrostatic protection, and shielding ground on the PCB reasonable
13. Is the location and connection method of single point grounding reasonable
14. Is the metal casing device that needs to be grounded correctly grounded
15. There should be no sharp corners or unreasonable right angles on the signal line
7. Is the layout and relative position of protective devices (such as TVS and PTC) reasonable
8. Have devices that may affect EMC experiments been placed according to design guidelines or successful experience references. For example, the reset circuit of the panel should be slightly closer to the reset button
9. Heavier components should be placed near the PCB support points or edges to reduce PCB warping
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